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GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Features :
262,144 words by 16 bits organization. Fast access time and cycle time. Dual CAS Input. Low power dissipation. Read-Modify-Write, RAS -Only Refresh,
CAS -Before-RAS Refresh, Hidden
Description :
The GLT44016 is a 262,144 x 16 bit high-performance CMOS dynamic random access memory. The GLT44016 offers Fast Page mode with Extended Data Output, and has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. The GLT44016 has symmetric address and accepts 512-cycle refresh in 8ms interval. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 512 x 16 bits within a page, with cycle times as short as 10ns. The GLT44016 is best suited for graphics, and DSP applications requiring high performance memories.
Refresh and Test Mode Capability. 512 refresh cycles per 8ms. Available in 40-Pin 400 mil SOJ and 40/44 Pin TSOP(II) Single 5.0V10% Power Supply. All inputs and Outputs are TTL compatible. Extended Data-Out(EDO) Page Mode operation.
HIGH PERFORMANCE Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) Max. CAS Access Time (tCAC)
25
28
30
35
40
50
25 ns 28 ns 30 ns 35 ns 40 ns 50 ns 13 ns 13 ns 16 ns 18 ns 20 ns 25 ns 10 ns 10 ns 12 ns 13 ns 15 ns 20 ns 45 ns 45 ns 60 ns 65 ns 70 ns 85 ns 8 ns 8 ns 10 ns 11 ns 12 ns 14 ns
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Pin Configuration : GLT44016 SOJ Top View TSOP(Type II) Top View
Pin Descriptions: Name A0 - A8
RAS UCAS LCAS WE OE
Function Address Inputs Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable Data Inputs / Outputs +5V Power Supply Ground No Connection
DQ1 - DQ16 VCC VSS NC
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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Absolute Maximum Ratings* Operating Temperature, TA (ambient)
.......................................-0C to +70C Storage Temperature(plastic)....-55C to +150C Voltage Relative to VSS...............-1.0V to + 7.0V Short Circuit Output Current......................50mA Power Dissipation......................................1.0W
*Note:Operation above Absolute Maximum Ratings can abversely affect device reliability.
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Capacitance*
TA=25C, VCC=5V10%, VSS=0V Symbol CIN1 CIN2 COUT Parameter Address Input
RAS , LCAS , UCAS , WE , OE
Max. Unit 5 7 7 pF pF pF
Data Input/Output
*Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l l l
CAS means UCAS and LCAS . All voltages are referenced to GND.
After power up, wait more than 100s and then, execute eight CAS -before-RAS or RAS -only refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
OE WE UCAS LCAS RAS
RAS CLOCK GENERATOR
CAS CLOCK GENERATOR
WE CLOCK GENERATOR
OE CLOCK GENERATOR
V CC V SS
Data I/O BUS COLUMN DECODERS REFRESH COUNTER
Y 0 - Y8 9 A0 A1 A7 A8 512 x 16
SENSE AMPLIFIERS
I/O BUFFER
. .
ADDRESS BUFFERS AND PREDECODERS
X 0 - x8
ROW DECODERS
512
MEMORY ARRAY
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Truth Table: GLT44016
Function Stanby Read: Word Read: Lower Byte Read: Upper Byte Write: Word(Early Write) Write: Lower Byte (Early) Write: Upper Byte (Early) Read Write EDO-Page- 1st Cycle Mode Read 2nd Cycle EDO-Page- 1st Cycle Mode Write 2nd Cycle EDO-Page- 1st Cycle Mode ReadWrite Hidden Refresh 2nd Cycle Read Write
RAS -Only Refresh CBR Refresh
RAS H L L L L L L L L L L L L
CASL HX L L H L L H L HL HL HL HL HL
CASH HX L H L L H L L HL HL HL HL HL
WE X H H H L L L HL H H L L HL
OE X L L L X X X LH L L X X LH
ADDRESS High-Z
DQs
Notes
ROW/COL Data Out ROW/COL Lower Byte,Data-Out Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,Data-Out ROW/COL Data-In ROW/COL Lower Byte,Data-In Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,Data-In ROW/COL Data-Out,Data-In ROW/COL Data-Out COL Data-Out
1,2 1 1 2 2 1,2
ROW/COL Data-In COL Data-In
ROW/COL Data-Out,Data-In
L LHL LHL L HL
HL L L H L
HL L L H L
HL H L X X
LH L X X X
COL
Data-Out,Data-In
1,2 1 2,3
ROW/COL Data-Out ROW/COL Data-In ROW High-Z High-Z
4
Notes:
1. These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active). 2. These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active ( UCAS or LCAS ).
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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DC and Operating Characteristics (1-2)
TA = 0C to 70C, VCC=5V10%, VSS=0V, unless otherwise specified.
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Sym.
ILI
Parameter
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) Operating Current, Random READ/WRITE
Test Conditions
0V VIN 5.5V (All other pins not under test=0V) 0V Vout 5.5V Output is disabled (Hiz) tRC = tRC (min.)
Access Time
Min.
-10
Typ
Max. Unit Notes
+10 A
ILO ICC1
-10 tRAC = 25ns tRAC = 28ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 50ns
+10 270 270 250 210 190 170 4
A
mA
1,2
ICC2
Standby Current,(TTL)
RAS , UCAS , LCAS at VIH other inputs VSS RAS cycling, UCAS , LCAS at VIH
tRC = tRC (min.) tRAC = 25ns tRAC = 28ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 50ns tRAC = 25ns tRAC = 28ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 50ns tRAC = 25ns tRAC = 28ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 50ns
mA
ICC3
Refresh Current,
RAS -Only
ICC4
Operating Current, EDO Page Mode
RAS at VIL, UCAS , LCAS address cycling:tPC=tPC(min.)
ICC5
Refresh Current,
RAS , UCAS , LCAS
address cycling: tRC=tRC (min.)
CAS Before RAS
270 270 250 210 190 170 270 270 250 210 190 170 270 270 250 210 190 170 2
mA
2
mA
1,2
mA
1
ICC6
Standby Current, (CMOS)
RAS VCC-0.2V, UCAS VCC-0.2V, LCAS VCC-0.2V, All other inputs VSS
mA
VIL VIH VOL VOH
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
-1 2.4 IOL = 4.2mA IOH = -5.0mA 2.4
+0.8 VCC+1 0.4
V V V V
3 3
Notes:
1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open. 2.ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in random Read/Write and EDO Fast Page Mode. 3.Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to exceed 20ns. All AC parameters are measured with VIL(min.)VSS and VIH(max.)VCC.
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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AC Characteristics
TA = 0C to 70C , VCC = 5 V 10%, VIH/VIL = 2.4/0.8 V, VOH/VOL = 2.0/0.8V
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
An initial pause of 100 s and 8 CAS -before- RAS or RAS -only refresh cycles are required after power-up. 25 28 30 35 40 50
Parameter Read or Write Cycle Time Read Modify Write Cycle Time Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes tRC tRWC tRP tRAS tRAC tCAC tAA tCLZ tCEZ tRSH tROH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tAR tRCS tRCH tRRH tWCS tWCH tWP tRWL tCWL 0 7 4 25 4 10 8 5 0 4 0 4 13 19 0 0 0 0 4 4 7 5 17 12 45 67 15 25 100k 25 8 13 0 5 0 7 4 25 4 10 8 5 0 4 0 4 13 19 0 0 0 0 4 4 7 5 17 12 45 67 15 28 100k 28 8 13 0 5 0 3 7 7 25 4.5 10 8 5 0 6 0 5 16 25 0 0 0 0 5 5 7 6 20 14 7 60 79 25 30 100k 30 10 16 0 3 8 8 30 5 11 9 5 0 7 0 6 18 30 0 0 0 0 6 6 8 7 24 17 8 65 86 25 35 100k 35 11 18 0 3 8 8 35 6 12 10 5 0 8 0 6 20 34 0 0 0 0 6 6 8 7 28 20 8 70 91 25 40 100k 40 12 20 0 3 8 8 42 8 13 11 5 0 9 0 7 25 35 0 0 0 0 6 6 8 7 36 25 8 85 106 30 50 ns ns ns 100k ns 50 14 25 ns 1,2,3
RAS Precharge Time RAS Pulse Width
Access Time from RAS Access Time from CAS Access Time from Column Address
ns 1,5,10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 4 8,9 7 1,5,6
CAS to Output Low-Z CAS to Output High-Z RAS Hold Time RAS Hold Time Referenced to OE CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time CAS to RAS Precharge Time Row Address Set-Up Time
Row Address Hold Time Column Address Set-Up Time Column Address Hold Time Column Address to RAS Lead Time Column Address Hold Time Referenced to RAS Read Command Set-Up Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS Write Command Set-Up Time Write Command Hold Time Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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AC Characteristics
25 Parameter Data Set-Up Time Data Hold Time Data Hold Time Referenced to RAS 28 30 35 40
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
50
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes tDS tDH tDHR tRWD tCWD tAWD tRPC tCPA tPC tPRWC tCP tRASP tOEA tOED tOEZ tOEH tDOH tREZ tWEZ tOCH tCHO tOEP tCSR tCHR tT tREF 5 3 5 4 3 3 8 8 8 5 6 1.5 50 8 7 10 7 0 4 19 36 19 24 0 15 10 35 3 25 100k 8 5 3 5 4 3 3 8 8 8 5 6 1.5 50 8 7 10 7 0 0 4 19 36 19 24 0 15 10 35 3 28 100k 8 7 3 6 5 3 3 8 8 8 10 7 1.5 50 8 7 10 7 12 39 4.5 30 100K 10 8 3 6 5 3 3 8 8 8 10 8 1.5 50 8 8 10 8 0 0 7 27 43 21 27 0 18 13 43 5 35 100k 11 8 3 7 5 3 3 8 8 8 10 8 1.5 50 8 8 10 8 0 8 32 49 23 30 0 20 15 45 6 40 100k 12 8 0 7 5 3 3 8 8 8 10 10 2 50 8 8 12 8 0 8 36 54 24 32 0 22 20 50 8 50 0 8 37 64 26 37 0 27 ns ns ns ns ns ns ns ns ns ns ns 100k ns 14 ns ns ns ns ns ns ns ns ns ns ns ns ns ms
RAS to WE E Delay Time CAS to WE Delay Time
Column Address to WE Delay Time
RAS to CAS Precharge Time
Access Time from CAS Precharge EDO Page Mode Cycle Time EDO Page Mode Read-Modify-Write Cycle Time
CAS Precharge Time (EDO Page Mode) RAS Pulse Width (EDO Page Mode Only)
Access Time from OE
OE to Data Delay Time OE to Output High-Z OE Command Hold Time
Data Output Hold after CAS low
RAS to Output High-Z WE to Output High-Z OE to CAS Hold Time CAS Hold Time to OE OE Precharge Time CAS Set-Up Time for CAS -before- RAS Cycle CAS Hold Time for CAS -before- RAS Cycle Transition Time
Refresh Period
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Notes:
1. Measure with a load equivalent to one TTL inputs and 50 pF. 2. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tAA dominant. 3. Assumes that tRAD tRAD (max.). If tRAD is greater than tRCD (max.), access time will be controlled by tCAC. 4. Either tRRH or tRCH must be satisfied for a Read Cycle. 5. Access time is determined by the longest of tCAA, tCAC and tCPA. 6. Assumes that tRAD tRAD (max.). 7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 9. tWCS (min.) must be satisfied in an Early Write Cycle. 10. tDS and tDH are referenced to the latter occurrence of CAS of WE .
tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 1.5 ns.
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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Read Cycle
tRC tRAS
VIH-
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
tRP
RAS
VIL-
tCRP
VIH-
tCSH tRCD tRSH tCAS
tCRP
CAS
VIL-
tASR Address
VIHVIL-
tRAD tRAH
tRAL tASC tCAH
COLUMN ADDRESS
ROW ADDRESS
tAR tRCS
VIH-
tRCH tRRH
WE
VIL-
tAA
VIH-
tCEZ tOEZ tOEA
OE
VIL-
tRAC DQ
VOHVOL-
tCAC tCLZ
DATA-OUT
Don't Care
Early Write Cycle NOTE : DOUT = Open
tRC tRP
VIH-
tRAS
RAS
VIL-
tCSH tCRP
VIH-
tRCD tCAS
tRSH
tCRP
CAS
VIL-
VIH-
tASR tRAH
ROW ADDRESS
tRAD tASC tCAH
COLUMN ADDRESS
tRAL
Address
VIL-
tCWL tRWL tAR
VIH-
tWCS
WE
VIL-
tWCR tWCH tWP
VIH-
OE
VIL-
tDHR tDS
VIH-
tDH
DATA - IN
DQ
VIL-
Don't Care
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Late Write Cycle ( OE Controlled Write)
VIHVIL-
NOTE : DOUT = Open
tRC tRP tRAS
RAS
tCSH tCRP CAS
VIHVIL-
tRCD tCAS
tRSH
tCRP
VIH-
tASR tRAH
ROW ADDRESS
tRAD tASC
tRAL tCAH
COLUMN ADDRESS
Address
VIL-
tCWL tRWL tRCS WE
VIHVIL-
tWP
OE
VIHVIL-
tOED tDS
tOEH tDH
COLUMN ADDRESS Don't Care
VIH-
DQ
VIL-
Read - Modify - Write Cycle
tRC tRP RAS
VIHVIL-
tRAS
tCRP CAS
VIHVIL-
tRCD
tRSH tCAS tCSH
tCRP
tASR Address
VIHVIL-
tRAD tASC tCAH
COLUMN ADDRESS
tRAH
ROW ADDR.
tAWD tCWD WE
VIHVIL-
tRWL tCWL tWP
OE
VIHVIL-
tOEA tCLZ tAA tCAC tOED tOEZ tDS
tDH
VALID DATA-IN Don't Care
DQ
VI/OHVI/OL-
tRAC
VALID DATA-OUT
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 10 -
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Fast Page Read Cycle
tRASP
VIH-
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
tRP
RAS
VIL-
tPC tCRP
VIH-
tPC tCAS tCP tRSH tCAS
tRCD
tCAS
tCP
CAS
VIL-
tRAD tCSH tASR tRAH tASC tCAH
COLUMN ADDRESS
tASC
tCAH
tASC
tCAH
Address
VIHVIL-
ROW ADDR.
COLUMN ADDRESS
COLUMN ADDRESS
tRCS
VIH-
tRCH
tRCS
tRCS
tRRH tRCH
WE
VIL-
tCAC tOEA
tCAC tOEA
VIH-
OE
VIL-
tRAC tCLZ DQ
VIHVIL-
tAA
tAA tOFF tCLZ tOEZ
tAA tOFF tCLZ tOEZ
tOFF tOEZ
VALID DATA-UOT
VALID DATA-UOT
VALID DATA-UOT
Don't Care
Fast Page Write Cycle
VIH-
NOTE : DOUT = Open
tRASP tRP tRHCP tPC tCRP tRCD tCAS tCP tPC tCAS tCP tRSH tCAS tRAD tASR tRAH tASC tCSH tCAH
COLUMN ADDRESS
RAS
VIL-
VIH-
CAS
VIL-
tASC
tCAH
tASC
COLUMN ADDRESS
tCAH
Address
VIHVIL-
ROW ADDR.
COLUMN ADDRESS
tWCS
VIH-
tWCH tWP tCWL
tWCS tWP
tWCH
tWCS
tWCH tWP
WE
VIL-
tCWL
tCWL tRWL
VIH-
OE
VIL-
tDS
VIH-
tDH
VALID DATA-IN
tDS
VALID DATA-IN
tDS
tDS
VALID DATA-IN
tDS
DQ
VIL-
Don't Care
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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Fast Page Mode Late Write Cycle
tRASP
VIH-
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
tRP tRHCP
RAS
VIL-
tCSH tCRP CAS
VIHVIL-
tPC tCAS tCP tCAS tCP tRSH tCAS tCRP
tRCD
tRAD tASR Address
VIHVILROW ADDR.
tCAH tASC
COLUMN ADDRESS
tRAH
tASC
COLUMN ADDRESS
tCAH
tASC
COLUMN ADDRESS
tRAL tCAH
tRCS
VIH-
tCWL tWP
tRCS
tCWL tWP
tRCS
tCWL tRWL tWP
WE
VIL-
tOEH
VIH-
tOEH
tOEH
OE
VIL-
tOED
VIH-
tDS
tDH
tOED tDS Hi-Z
tDH
tOED tDS Hi-Z
tDH
Hi-Z
DQ
VIL-
VALID DATA-IN
VALID DATA-IN
VALID DATA-IN
Don't Care
Fast Page Read - Modify - Write Cycle
tRASP
VIH-
tRP
RAS
tCSH tRSH tCAS
VIL-
tRCD
VIH-
tCAS
tCP
tCRP
CAS
VIL-
tASR
VIH-
tRAD tRAH tASC
tCAH tASC
COL. ADDR. COL. ADDR.
tPRWC tRAL tCAH
Address
VIL-
ROW ADDR.
tRCS
VIH-
tCWL tCWD tAWD tRWD tWP tCWD tAWD tCPWD
WE
tRWL tCWL tWP
VIL-
tOEH tDH tOED tOEZ tDS tOEA tCAC tAA tOED tOEZ tDH tDS
VIH-
OE
tOEA tCAC tAA tRAC
VIL-
VI/OH-
DQ
VI/OL-
tCLZ
VALID DATA-OUT VALID DATA-IN
tCLZ
VALID DATA-OUT VALID DATA-IN Don't Care
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
CAS Before RAS Refresh Cycle
tRC tRAS
VIH-
tRC tRP tRAS tRP
RAS
VIL-
tCSR CAS
VIHVIL-
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
RAS -Only Refresh Cycle
tRC tRAS RAS
VIHVIL-
tRC tRP tRAS tRP
tCRP CAS
VIHVIL-
tRPC
tCRP
tASR
VIH-
tRAH
ROW
tASR
tRAH
ROW
Address
VIL-
Hidden Refresh Cycle ( Read )
tRC tRAS RAS
VIHVIL-
tRC tRP tRAS tRP
tCRP
VIH-
tRCD
tRSH
tCHR
CAS
VIL-
tRAD tASR Address
VIHVIL-
tRAL tASC
COLUMN ADDRESS
tCAH
tCAH
ROW ADDRESS
tRCS
VIH-
tWHR
WE
VIL-
tAA tOEA
VIH-
OE
VIL-
tCAC tRAC DQ
VIHVIL-
tCLZ
tOEZ
DATA-OUT
tOFF
OPEN
Don't Care
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Hidden Refresh Cycle ( Write )
VIHVIL-
NOTE : DOUT =Open
tRC tRAS tRP tRAS tRC tRP
RAS
tCRP
VIH-
tRCD
tRSH
tCHR
CAS
VIL-
tRAD tASC Address
VIHVIL-
tCAH
tASC
COLUMN ADDRESS
tCAH
ROW ADDRESS
tWCS
VIH-
tWCH tWP
WE
VIL-
VIH-
OE
VIL-
tDS DQ
VIHDATA-IN
tDH
VIL-
Don't Care
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
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GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
CAS - Before RAS Refresh Counter Test Cycle
tRAS RAS VILVIHCAS VILVIH-
tRP
tCSR
tCHR
tCPT
tRSH tCAS tRAL tCAH
tASC AddressVIHVILCOLUMN ADDRESS
Read Cycle
VIHWE VIL-
tWRP
tWRH
tAA tCAC tRCS tOEA tCLZ tOEZ
VALID DATA-OUT
tRRH tRCH
OE VIL-
VIH-
tCEZ
DQ VOL-
VOH-
Write Cycle
VIHWE VIL-
tWRP
tWRH tWCS
tRWL tCWL tWCH tWP
OE VIL-
VIH-
tDS
VIHDQ VIL-
tDH
VALID DATA-IN
OPEN tRCS
Read-Modify-Write
WE VILVIH-
tAWD tCWD tCAC tAA tOEA tOED tCLZ tOEZ
tCWL tRWL tWP
OE VIL-
VIH-
tDH tDS
DQ VI/OL-
VI/OH-
VALID DATA-OUT
VALID DATA-IN
Don't Care
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 15 -
G -LINK
Ordering Information
Part Number
GLT44016-25J4 GLT44016-28J4 GLT44016-30J4 GLT44016-35J4 GLT44016-40J4 GLT44016-50J4 GLT44016-25TC GLT44016-28TC GLT44016-30TC GLT44016-35TC GLT44016-40TC GLT44016-50TC
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
SPEED
25ns 28ns 30ns 35ns 40ns 50ns 25ns 28ns 30ns 35ns 40ns 50ns
POWER
Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal
FEATURE
EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO EDO
PACKAGE
40L 400mil SOJ 40L 400mil SOJ 40L 400mil SOJ 40L 400mil SOJ 40L 400mil SOJ 40L 400mil SOJ 44L 400mil TSOP 44L 400mil TSOP 44L 400mil TSOP 44L 400mil TSOP 44L 400mil TSOP 44L 400mil TSOP
Parts Numbers (Top Mark) Definition :
GLT 4 40
4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM -SRAM 064 : 8K 256 : 256K 512 : 512K 100 : 1M -DRAM 10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note
16 - 40 J4
CONFIG. 04 : x04 08 : x08 16 : x16 32 : x32 SPEED -SRAM 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -DRAM 25 : 25ns 30 : 30ns 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns PACKAGE T : PDIP(300mil) TS : TSOP(Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP
VOLTAGE Blank : 5V L : 3.3V M : Mix Voltage
Note : CUCDROM , HUHDD. Example : 1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type. 2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 16 -
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Package Information
40/44 Lead Thin Small Outline Package SOJ
40/44 Lead Thin Small Outline Package TSOP(Type II)
G-Link Technology Corporation
2701Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan.
- 17 -

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